NCP5355
5V
V S
5 V Regulator
5V
BST
Overtemp.
Shutdown
5V
5V
5V
V S
5V
Level Shift
TG
?
+
UVLO
5V
Driver
100 k
DRN
8.0/7.0 V
Nonoverlap
30 k
PGND
5V
30 ns
5V
20 k
CO
5V
Nonoverlap
30 ns
20 k
2.0 m A
5V
5V
5V
V S
V S
30 k
EN
PACKAGE PIN DESCRIPTION
Figure 1. Block Diagram
Level Shift
Driver
BG
Pin
1
2
3
4
5
6
7
8
Pin Symbol
DRN
TG
BST
CO
EN
V S
BG
PGND
Description
The switching node common to the high and low?side FETs. The high?side (TG) driver and supply (BST)
are referenced to this pin.
Driver output to the high?side MOSFET gate.
Bootstrap supply voltage input. In conjunction with an internal diode to V S , a 0.1 m F to 1.0 m F ceramic
capacitor connected between BST and DRN develops supply voltage for the high?side driver (TG).
Logic level control input produces complementary output states ? no inversion at TG; inversion at BG.
Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation
ensues. No connect defaults EN high. Note: maximum high input is 5.0 V.
Power supply input. A 0.1 m F to 1.0 m F ceramic capacitor should be connected from this pin to PGND.
Driver output to the low?side (synchronous rectifier) MOSFET gate.
Ground.
http://onsemi.com
2
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